Reducing power consumption of electronic devices has become increasingly important, particularly for battery powered devices such as laptop computers, personal digital assistants, cellular phones, MP3 players and other devices. Analog-to-digital converters (ADCs) are commonly used in these electronic devices to transform analog signals to digital signals. Relative to other components, ADCs tend to consume a significant amount of power. Therefore, reducing the power consumption of the ADCs is important for reducing the overall power consumption of the system. The ADC may include a pipelined ADC that utilizes multiple stages. Each stage employs a sample and hold circuit that samples an analog input voltage Vin to the pipelined ADC or a residue voltage Vres from a prior stage.
Referring now to FIG. 1, a typical pipelined ADC 10 is shown. The ADC 10 includes a plurality of stages 12-1, 12-2, and 12-3 (collectively stages 12) that are cascaded in series. Although three stages 12-1, 12-2, and 12-3 are shown, the pipelined ADC 10 may include additional or fewer stages. Some of the ADC stages 12 include a sample and integrate (or hold) module 14 that samples and integrates (or holds) the analog input signal Vin or the residue signal Vres from a prior stage.
A low resolution A/D subconverter module 16 quantizes the held analog signal to a resolution of Bi bits where i corresponds to the current stage of the pipelined A/D converter 10. The number of bits per stage Bi and/or the number of stages may be determined in part by the desired sampling rate and resolution. The output of the A/D subconverter module 16 is supplied to a low-resolution D/A subconverter module 18 that converts the resulting digital output signal back into an analog representation.
The D/A subconverter module 18 may have a resolution that is equivalent to that of the corresponding A/D subconverter module 16 of the same stage. A difference module 20 subtracts the analog output from the D/A subconverter module 18 from the voltage input Vin to generate a residue signal Vres. The residue signal Vres is equal to the difference between the held analog signal (Vin or Vres from the prior stage) and the reconstructed analog signal.
An amplifier 22 may be used to amplify the residue signal. The amplified residue signal is output to the next stage 12-2 of the pipelined ADC 10. The first ADC stage 12-1 of the pipelined ADC 10 operates on a most current analog input sample while the second ADC stage 12-2 operates on the amplified residue of the prior input sample. The third stage 12-3 operates on the amplified residue output by the second ADC stage 12-2.
The concurrency of operations allows a conversion speed that is determined by the time it takes in one stage. Once a current stage has completed operating on the analog input sample received from the prior stage, the current stage is available to operate on the next sample.